參數(shù)資料
型號: A6841ELW-T
廠商: Allegro MicroSystems, Inc.
英文描述: DABiC-5 8-Bit Serial Input Latched Sink Drivers
中文描述: 達(dá)比奇- 5 8位串行輸入鎖存灌電流驅(qū)動器
文件頁數(shù): 4/10頁
文件大?。?/td> 248K
代理商: A6841ELW-T
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
D
2
Timing Requirements and Speci
fi
cations
(Logic Levels are V
DD
and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT ENABLE
OUT
N
50%
SERIAL
DATAOUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTP UTS E NABLE D
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
OUTPUT ENABLE
OUT
N
DATA
10%
50%
dis(BQ)
t
en(BQ)
t
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the speci
fi
ed maxi-
mum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
S
erial Data present at the input is transferred to the shift register on the logical
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the input prior to the rising edge of the
CLOCK input waveform.
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applica-
tions where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
Key
A
B
C
D
E
Description
Symbol
t
su(D)
t
h(D)
t
w(CH)
t
su(C)
t
w(STH)
Time (ns)
25
25
50
100
50
Data Active Time Before Clock Pulse (Data Set-Up Time)
Data Active Time After Clock Pulse (Data Hold Time)
Clock Pulse Width
Time Between Clock Activation and Strobe
Strobe Pulse Width
相關(guān)PDF資料
PDF描述
A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841SA-T DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841SLW-T DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841SLW-20-T DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841ELW-20-T DABiC-5 8-Bit Serial Input Latched Sink Drivers
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