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參數(shù)資料
| 型號： | A6833SEP-T |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | DABiC-5 32-Bit Serial Input Latched Sink Drivers |
| 中文描述： | 達(dá)比奇- 5 32位串行輸入鎖存灌電流驅(qū)動器 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 174K |
| 代理商： | A6833SEP-T |
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
D
2
Timing Requirements and Specifications
(Logic Levels are V
DD
and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT ENABLE
OUT
N
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
HIGH = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
OUTPUT ENABLE
OUT
N
DATA
10%
50%
dis(BQ)
t
en(BQ)
t
LOW = ALL OUTPUTS BLANKED (DISABLED)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specified maximum clock frequency.
S
erial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
Key
A
B
C
D
E
Description
Symbol
t
su(D)
t
h(D)
t
w(CH)
t
su(C)
t
w(STH)
Time (ns)
25
25
50
100
50
Data Active Time Before Clock Pulse (Data Set-Up Time)
Data Active Time After Clock Pulse (Data Hold Time)
Clock Pulse Width
Time Between Clock Activation and Strobe
Strobe Pulse Width
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A6833SEP-T | 制造商:Allegro MicroSystems LLC 功能描述:Driver IC Number of Drivers:32 |
| A6833SEPTR-T | 功能描述:IC SINK DVR 32BIT LATCH 44-PLCC RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 內(nèi)部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:高端/低端驅(qū)動器 輸入類型:SPI 輸出數(shù):8 導(dǎo)通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
| A683K15X7RF5TAA | 功能描述:CAP CER 0.068UF 50V X7R AXIAL RoHS:是 類別:電容器 >> 陶瓷 系列:單軸 標(biāo)準(zhǔn)包裝:4,000 系列:- 電容:1000pF 電壓 - 額定:50V 容差:±10% 溫度系數(shù):X7R 安裝類型:表面貼裝，MLCC 工作溫度:-55°C ~ 125°C 應(yīng)用:自動 額定值:AEC-Q200 封裝/外殼:0805（2012 公制） 尺寸/尺寸:0.079" L x 0.047" W（2.00mm x 1.20mm） 高度 - 座高（最大）:- 厚度（最大）:- 引線間隔:- 特點(diǎn):- 包裝:帶卷 (TR) 引線型:- |
| A683K15X7RF5UAA | 功能描述:CAP CER 0.068UF 50V X7R AXIAL RoHS:是 類別:電容器 >> 陶瓷 系列:單軸 標(biāo)準(zhǔn)包裝:4,000 系列:- 電容:1000pF 電壓 - 額定:50V 容差:±10% 溫度系數(shù):X7R 安裝類型:表面貼裝，MLCC 工作溫度:-55°C ~ 125°C 應(yīng)用:自動 額定值:AEC-Q200 封裝/外殼:0805（2012 公制） 尺寸/尺寸:0.079" L x 0.047" W（2.00mm x 1.20mm） 高度 - 座高（最大）:- 厚度（最大）:- 引線間隔:- 特點(diǎn):- 包裝:帶卷 (TR) 引線型:- |
| A683K20X7RH5TAA | 功能描述:CAP CER 0.068UF 100V 10% AXIAL RoHS:是 類別:電容器 >> 陶瓷 系列:單軸 標(biāo)準(zhǔn)包裝:4,000 系列:- 電容:1000pF 電壓 - 額定:50V 容差:±10% 溫度系數(shù):X7R 安裝類型:表面貼裝，MLCC 工作溫度:-55°C ~ 125°C 應(yīng)用:自動 額定值:AEC-Q200 封裝/外殼:0805（2012 公制） 尺寸/尺寸:0.079" L x 0.047" W（2.00mm x 1.20mm） 高度 - 座高（最大）:- 厚度（最大）:- 引線間隔:- 特點(diǎn):- 包裝:帶卷 (TR) 引線型:- |
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