- 您現在的位置：買賣IC網 > PDF目錄375156 > A6811SEP (Allegro MicroSystems, Inc.) DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER PDF資料下載
參數資料
| 型號： | A6811SEP |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| 中文描述： | 達比奇第四，12位串行輸入，鎖存源驅動 |
| 文件頁數： | 5/8頁 |
| 文件大?。?/td> | 156K |
| 代理商： | A6811SEP |
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
BLANKING
OUT
N
Dwg. WP-030
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
90%
r
t
f
t
A.
Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
.........................................
25 ns
B.
Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
...............................................
25 ns
C.
Clock Pulse Width, t
w(CH)
...............................................
50 ns
D.
Time Between Clock Activation and Strobe, t
su(C)
.......
100 ns
E.
Strobe Pulse Width, t
w(STH)
.............................................
50 ns
NOTE
–
Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
相關PDF資料 |
PDF描述 |
|---|---|
| A6811SLW | DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| A6812 | DABiC-IV,20-Bit Serial-Input, Latched Source Driver(驅動真空熒光顯示器的DABiC-IV,20位鎖存源驅動器) |
| A6817SEP | ADDRESSABLE 28-LINE DECODER/DRIVER |
| A6817 | Addressable 28-Line Decoder/Driver(用于噴墨打印機的可設定位址的28線譯碼器/驅動器) |
| A6821 | DABiC-5 8-Bit Serial Input Latched Sink Drivers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| A6811SLW | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| A6812 | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:DABiC-IV, 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| A68120C0GL5 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Axial Leaded Multilayer Ceramic Capacitors for General Purpose Class 1, Class 2 and Class 3, 50 VDC, 100 VDC, 200 VDC, 500 VDC |
| A6812EA | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:DABiC-IV, 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| A6812EEP | 功能描述:IC SOURCE DRVR 20BIT SER 28PLCC RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅動器 - 內部開關 系列:- 標準包裝:1,000 系列:- 類型:高端/低端驅動器 輸入類型:SPI 輸出數:8 導通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。