參數(shù)資料
型號: A67L8336E-3.5
廠商: AMIC Technology Corporation
英文描述: 512K X 18, 256K X 36 LVTTL, Pipelined ZeBL SRAM
中文描述: 為512k × 18,256 × 36 LVTTL,流水線ZeBL的SRAM
文件頁數(shù): 12/18頁
文件大?。?/td> 255K
代理商: A67L8336E-3.5
A67L9318/A67L8336
PRELIMINARY (July, 2005, Version 0.0)
12
AMIC Technology, Corp.
AC Characteristics
(Note 4)
(0
°
C
T
A
70
°
C, VCC = +3.3V
±
5%)
-2.6
-2.8
-3.2
-3.5
-3.8
-4.2
Unit
Note
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
t
KHKH
Clock cycle time
4.0
-
4.4
-
5.0
-
6.0
-
6.7
-
7.5
-
ns
t
KF
Clock frequency
-
250
-
227
-
200
-
166
-
150
-
133
MH
t
KHKL
Clock HIGH time
1.7
-
2.0
-
2.0
-
2.2
-
2.5
-
3.0
-
ns
t
KLKH
Clock LOW time
1.7
-
2.0
-
2.0
-
2.2
-
2.5
-
3.0
-
ns
Output Times
t
KHQV
Clock to output valid
-
2.6
-
2.8
-
3.2
-
3.5
-
3.8
-
4.2
ns
t
KHQX
Clock to output invalid
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
t
KHQX1
Clock to output in Low-Z
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
1,2,3
t
KHQZ
Clock to output in High-Z
1.5
2.6
1.5
2.8
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.5
ns
1,2,3
t
GLQV
OE
to output valid
-
2.6
-
2.8
-
3.2
-
3.5
-
3.8
-
4.2
ns
4
t
GLQX
OE
to output in Low-Z
0
-
0
-
0
-
0
-
0
-
0
-
ns
1,2,3
t
GHQZ
OE
to output in High-Z
-
2.6
-
2.8
-
3.0
-
3.0
-
3.0
-
3.5
ns
1,2,3
Setup Times
t
AVKH
Address
1.2
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
5
t
EVKH
Clock enable (
CEN
)
1.2
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
5
t
CVKH
Control signals
1.2
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
5
t
DVKH
Data-in
1.2
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
5
Hold Times
t
KHAX
Address
0.3
-
0.4
-
0.4
-
0.5
-
0.5
-
0.5
-
ns
5
t
KHEX
Clock enable (
CEN
)
0.3
-
0.4
-
0.4
-
0.5
-
0.5
-
0.5
-
ns
5
t
KHCX
Control signals
0.3
-
0.4
-
0.4
-
0.5
-
0.5
-
0.5
-
ns
5
t
KHDX
Data-in
0.3
-
0.4
-
0.4
-
0.5
-
0.5
-
0.5
-
ns
5
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured
±
200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/
LD
is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/
LD
is LOW) to remain enabled.
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