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參數(shù)資料
| 型號： | A67L7336E-45 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| 中文描述： | 256 × 16/18，128K的X 32/36 LVTTL，管線數(shù)據(jù)庫管理員的SRAM |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 272K |
| 代理商： | A67L7336E-45 |
A67L8316/A67L8318/
A67L7332/A67L7336 Series
PRELIMINARY (December, 1999, Version 0.1)
16
AMIC Technology, Inc.
NOP, STALL and Deselect Cycles
Note :
1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates
CEN
being used to create a “pause.” A WRITE
is not performed during this cycle.
2. For this waveform, ZZ and
OE
are tied LOW.
3.
CE
represents three signals. When
CE
= 0, it represents
CE
= 0,
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The
most recent data may be from the input data register.
2
CE
= 0, CE2 = 1.
A3
A2
A1
A4
A5
Q(A5)
D(A4)
Q(A3)
Q(A2)
D(A1)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
: Don't Care
: Undefined
1
2
3
4
5
t
KHQX
t
KHQZ
6
7
8
9
10
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
COMMAND
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| A67L7336E-5 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-6 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L8316 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L8316E-45 | T1 CABLE RJ48-RJ48 CROSS PINNED 10 FEET |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A67L7336E-5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16/18. 128K X 32/36 LVTTL. Pipelined DBA SRAM |
| A67L8316 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L83161 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
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