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參數(shù)資料
| 型號(hào)： | A67L73361E-12 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| 中文描述： | 256 × 16/18，128K的X 32/36 LVTTL，流通過(guò)數(shù)據(jù)庫(kù)管理員的SRAM |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大小： | 271K |
| 代理商： | A67L73361E-12 |
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A67L83161/A67L83181/
A67L73321/A67L73361 Series
PRELIMINARY (September, 1999, Version 0.1)
12
AMIC Technology, Inc.
AC Characteristics
(Note 4)
(0
°
C
≤
T
A
≤
70
°
C, VCC = 3.3V
±
5%)
-10
-11
-12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
Clock
t
KHKH
Clock cycle time
10
-
11
-
12
-
ns
t
KF
Clock frequency
-
100
-
90
-
83
MHz
t
KHKL
Clock HIGH time
3.0
-
3.5
-
4.0
-
ns
t
KLKH
Clock LOW time
3.0
-
3.5
-
4.0
-
ns
Output Times
t
KHQV
Clock to output valid
-
10
-
11
-
12
ns
t
KHQX
Clock to output invalid
3.0
-
3.0
-
3.0
-
ns
t
KHQX1
Clock to output in Low-Z
4.0
-
4.0
-
4.0
-
ns
1,2,3
t
KHQZ
Clock to output in High-Z
1.5
5.0
1.5
5.0
1.5
5.0
ns
1,2,3
t
GLQV
OE
to output valid
-
5.0
-
5.0
-
5.0
ns
4
t
GLQX
OE
to output in Low-Z
0
-
0
-
0
-
ns
1,2,3
t
GHQZ
OE
to output in High-Z
-
5.0
-
5.0
-
5.0
ns
1,2,3
Setup Times
t
AVKH
Address
2.5
-
2.5
-
2.5
-
ns
5
t
EVKH
Clock enable (
CEN
)
2.5
-
2.5
-
2.5
-
ns
5
t
CVKH
Control signals
2.5
-
2.5
-
2.5
-
ns
5
t
DVKH
Data-in
2.5
-
2.5
-
2.5
-
ns
5
Hold Times
t
KHAX
Address
0.5
-
0.5
-
0.5
-
ns
5
t
KHEX
Clock enable (
CEN
)
0.5
-
0.5
-
0.5
-
ns
5
t
KHCX
Control signals
0.5
-
0.5
-
0.5
-
ns
5
t
KHDX
Data-in
0.5
-
0.5
-
0.5
-
ns
5
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured
±
200mV from steady state voltage.
4.
OE
can be considered a “Don’t Care” during WRITE; however, controlling
OE
can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/LD is LOW) to remain enabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A67L83161 | 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L83181E-10 | 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L83181E-11 | 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L83181E-12 | 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L8318 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A67L7336E-45 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16/18. 128K X 32/36 LVTTL. Pipelined DBA SRAM |
| A67L8316 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
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