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參數(shù)資料
| 型號： | A67L7332E-5 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| 中文描述： | 256 × 16/18，128K的X 32/36 LVTTL，管線數(shù)據(jù)庫管理員的SRAM |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 272K |
| 代理商： | A67L7332E-5 |
A67L8316/A67L8318/
A67L7332/A67L7336 Series
PRELIMINARY (December, 1999, Version 0.1)
6
AMIC Technology, Inc.
Pin Description (continued)
Pin No.
Symbol
Description
LQFP (X16/X18)
LQFP (X32/X36)
87
87
CEN
Synchronous Clock Enable : This active low input permits
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
64
64
ZZ
Snooze Enable : This active high asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active,
all other inputs are ignored.
88
88
R/
W
Read/Write : This active input determines the cycle type
when ADV/LD is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be
converted into WRITEs (and vice versa) other than by
loading a new address. A LOW on this pin permits BYTE
WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
(a) 58, 59, 62, 63,
68, 69, 72, 73
(b) 8,9,12,13, 18,
19, 22,23
(a) 52, 53, 56, 57,
58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9,
12, 13,
(d) 18, 19, 22, 23,
24, 25, 28, 29
I/Oa
I/Ob
I/Oc
I/Od
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;
Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must
meet setup and hold times around CLK rising edge.
74
24
51
80
1
30
NC/I/Oa
NC/I/Ob
NC/I/Oc
NC/I/Od
No Connect/Data Bits : On the X16/32 version, these pins
are no connect (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the X18/36
version, these bits are I/Os.
31
31
MODE
Mode : This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating.
1, 2, 3, 6, 7, 25,
28, 29, 30, 38, 39,
42, 43, 51, 52, 53,
56, 57, 75, 78, 79,
83, 84, 95, 96
38,39,42,43
83,84
NC
No Connect : These pins can be left floating or connected to
GND to minimize thermal impedance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A67L7332E-6 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-45 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-5 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7336E-6 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A67L7332E-6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7332SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16/18. 128K X 32/36 LVTTL. Pipelined DBA SRAM |
| A67L7336 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L73361 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L73361E-10 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
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