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參數(shù)資料
| 型號(hào)： | A67L0636E |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| 中文描述： | 2米x 18，100萬米鼠36 LVTTL，流水線ZeBL的SRAM |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 253K |
| 代理商： | A67L0636E |
A67L1618/A67L0636 Series
PRELIMINARY (March, 2005, Version 0.1)
16
AMIC Technology, Corp.
NOP, STALL and Deselect Cycles
Note :
1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates
CEN
being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and
OE
are tied LOW.
3.
CE
represents three signals. When
CE
= 0, it represents
CE
= 0,
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
2
CE
= 0, CE2 = 1.
A3
A2
A1
A4
A5
Q(A5)
D(A4)
Q(A3)
Q(A2)
D(A1)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
: Don't Care
: Undefined
1
2
3
4
5
t
KHQX
t
KHQZ
6
7
8
9
10
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
COMMAND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A67L0636E-2.6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| A67L0636E-2.6F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| A67L0636E-2.8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| A67L0636E-2.8F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| A67L0636E-3.2 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
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