- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375150 > A63P8336E-4.2 (AMIC Technology Corporation) 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output PDF資料下載
參數(shù)資料
| 型號： | A63P8336E-4.2 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| 中文描述： | 256 × 36位同步高的Burst計(jì)數(shù)器和流水線數(shù)據(jù)輸出高速SRAM |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 257K |
| 代理商： | A63P8336E-4.2 |
A63P8336
PRELIMINARY
(July, 2005, Version 0.0)
12
AMIC Technology, Corp.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS
A1
A2
A3
OE
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
High-Z
DIN
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
t
ADSH
t
ADSS
ADSC extends burst
GW
CE
(NOTE *2)
ADV
D(A1)
D(A2+1)
D(A3+2)
DOUT
BURST READ
Single WRITE
Extended BURST WRITE
t
OEHZ
t
DH
t
DS
(NOTE *3)
(NOTE *4)
ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
t
WH
t
WS
BWE,BW1-BW4
(NOTE *5)
(NOTE *1)
Write Timing
Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE. As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
*4. ADV must be HIGH to permit a Write to the loaded address.
*5. Byte Write enables are decided by means of a Write truth table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A63P8336 | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-2.6 | surface mount silicon Zener diodes |
| A64E06161 | 1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-70 | 1M X 16 Bit Low Voltage Super RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A63QDB891X | 制造商:Panasonic Industrial Company 功能描述:CRT |
| A63R | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:ACMOS ENABLE/DISABLE TRISTATE OUTPUT |
| A63RA | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:8 Pin DIP Tri-State ACMOS Clock Oscillators |
| A63RA-125 | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:8 Pin DIP Tri-State ACMOS Clock Oscillators |
| A63RD | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:ACMOS ENABLE/DISABLE TRISTATE OUTPUT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。