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參數(shù)資料
| 型號(hào)： | A63P8336E-2.6 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | surface mount silicon Zener diodes |
| 中文描述： | 表面貼裝硅穩(wěn)壓二極管 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 257K |
| 代理商： | A63P8336E-2.6 |
A63P8336
256K X 36 Bit Synchronous High Speed SRAM with
Burst Counter and Pipelined Data Output
Preliminary
PRELIMINARY (July, 2005, Version 0.0)
1
AMIC Technology, Corp.
Features
Fast access times: 2.6/2.8/3.2/3.5/3.8/4.2 ns
(250/227/200/166/150/133 MH
Z
)
Single +2.5V+10% or +2.5V-5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Registered output for pipelined applications
General Description
The A63P8336 is a high-speed SRAM containing 9M bits
of bit synchronous memory, organized as 256K words by
36 bits.
The
A63P8336
combines
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 256KX36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A17), all data inputs (I/O
1
- I/O
36
), active LOW chip enable
(
CE ), two additional chip enables (CE2, CE2 ), burst
control inputs ( ADSC , ADSP , ADV ), byte write enables
( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write
(GW ). Asynchronous inputs include output enable (OE ),
clock (CLK), BURST mode (MODE) and SLEEP mode
(ZZ).
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
advanced
synchronous
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63P8336
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A63P8336E-3.2 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-3.2F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-3.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-3.5F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-3.8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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