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參數(shù)資料
| 型號： | A62S6308V-70S |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 64K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 64K的× 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 179K |
| 代理商： | A62S6308V-70S |
A62S6308 Series
(October, 1998, Version 2.0)
10
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
30pF
* Including scope and jig.
* Including scope and jig.
C
L
TTL
5pF
C
L
TTL
Data Retention Characteristics
(T
A
= 0
°
C to + 70
°
C or -25
°
C to 85
°
C)
Figure 1. Output Load
Figure 2. Output Load for t
CLZ1
,
t
CLZ2
, t
OHZ
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
WHZ
, and t
OW
Symbol
Parameter
Min.
Max.
Unit
Conditions
V
DR1
2.0
3.6
V
CE1
≥
VCC - 0.2V
V
DR2
VCC for Data Retention
2.0
3.6
V
CE2
≤
0.2V
CE1
≥
VCC - 0.2V or
CE1
≤
0.2V
I
CCDR1
S-Version
-
10*
μ
A
VCC = 2.0V
CE1
≥
VCC - 0.2V
CE2
≥
VCC - 0.2V
V
IN
≥
0V
Data Retention Current
SI-Version
-
20**
I
CCDR2
S-Version
-
10*
μ
A
VCC = 2.0V
CE2
≤
0.2V
V
IN
≥
0V
SI-Version
-
20**
t
CDR
Chip Disable to Data Retention Time
0
-
ns
t
R
Operation Recovery Time
t
RC
-
ns
See Retention Waveform
t
VR
VCC Rise Time from Data Retention Voltage
to Operating Voltage
5
-
ms
** A62S6308-70S/10S
* A62S6308-70SI/10SI
I
CCDR
: Max. 3
μ
A at T
A
= 0
°
C + 40
°
C
I
CCDR
: Max. 3
μ
A at T
A
= 0
°
C + 40
°
C
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| A62S6308X-70SI | 64K X 8 BIT LOW VOLTAGE CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A62S6308V-70SI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:64K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62S6308X-10S | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:64K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62S6308X-10SI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:64K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62S6308X-70S | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:64K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62S6308X-70SI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:64K X 8 BIT LOW VOLTAGE CMOS SRAM |
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