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參數(shù)資料
| 型號(hào)： | A62L256R-55LLU |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 32K的× 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 146K |
| 代理商： | A62L256R-55LLU |
A62L256 Series
PRELIMINARY (November, 2001, Version 1.4)
9
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 2
(6)
(Chip Enable Controlled)
t
WC
Address
CE
D
IN
t
DH
t
DW
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
t
WHZ7
t
WP2
t
AS1
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low CE and a low WE .
3. t
WR
is measured form the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. t
CW
is measured from the later of CE going low to the end of Write.
6. OE level is high or low.
7. Transition is measured
±
500mV from steady. This parameter is sampled and not 100% tested.
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| A62L256V-55LL | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
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| A62L256V-70LL | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-70LLU | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256 | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
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| A62L256R-70LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256R-70LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-55LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-55LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-70LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
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