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參數(shù)資料
| 型號： | A62L256R-55LL |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 32K的× 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 146K |
| 代理商： | A62L256R-55LL |
A62L256 Series
PRELIMINARY (November, 2001, Version 1.4)
10
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0V, VCC
Input Rise And Fall Time
5 ns
Input and Output Timing Reference Levels
VCC/2
Output Load
See Figure 1
30pF
* Including scope and jig.
C
L
Figure 1. Output Load
Data Retention Characteristics
(T
A
= 0
°
C to 70
°
C or -40oC to +85oC)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
V
DR
VCC for Data Retention
2.0
-
3.6
V
CE
≥
VCC - 0.2V
LL-version
-
0.02
0.5
I
CCDR
Data Retention Current
LLU-version
-
0.02
2
μ
A
VCC = 2V,
CE
≥
VCC - 0.2V
V
IN
≥
0V
t
CDR
Chip Disable to Data Retention Time
0
-
ns
See Retention Waveform
t
R
Operation Recovery Time
t
RC
-
ns
Typical values are measured at T
A
= 25
°
C.
Low VCC Data Retention Waveform
VCC
t
CDR
V
IH
3.0V
t
R
V
IH
3.0V
DATA RETENTION MODE
VCC
≥
2.0V
CE
≥
VCC - 0.2V
CE
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| A62L256R-55LLU | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| A62L256R-55LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256R-70LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256R-70LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-55LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-55LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
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