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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | A54SX72A-FFG256 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 26/108闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA SX-A 108K 256-FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | SX-A |
| LAB/CLB鏁�(sh霉)锛� | 6036 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 203 |
| 闁€鏁�(sh霉)锛� | 108000 |
| 闆绘簮闆诲锛� | 2.25 V ~ 5.25 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 256-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FPBGA锛�17x17锛� |
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SX-A Family FPGAs
2- 4
v5.3
Table 2-8 AC Specifications (5 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT 鈮� 1.4
1
鈥�44
鈥�
mA
1.4
鈮� V
OUT < 2.4
1, 2
(鈥�44 + (VOUT 鈥� 1.4)/0.024)
鈥�
mA
3.1 < VOUT < VCCI
1, 3
鈥�
鈥�
(Test Point)
VOUT = 3.1
3
鈥撯€�142
mA
IOL(AC)
Switching Current Low
VOUT 鈮� 2.2
1
95
鈥�
mA
2.2 > VOUT > 0.55
1
(VOUT/0.023)
鈥�
mA
0.71 > VOUT > 0
1, 3
鈥�
鈥�
(Test Point)
VOUT = 0.71
3
鈥�
206
mA
ICL
Low Clamp Current
鈥�5 < VIN 鈮� 鈥�1
鈥�25 + (VIN + 1)/0.015
鈥�
mA
slewR
Output Rise Slew Rate
0.4 V to 2.4 V load 4
15
V/ns
slewF
Output Fall Slew Rate
2.4 V to 0.4 V load 4
15
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. 鈥淪witching Current High鈥� specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Output
Buffer
1/2 in. max.
50 pF
Pin
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A54SX72A-FFGG256 | IC FPGA SX-A 108K 256-FBGA |
| AGL600V5-CS281I | IC FPGA 1KB FLASH 600K 281-CSP |
| M1AGL600V5-CSG281I | IC FPGA 1KB FLASH 600K 281-CSP |
| M1AGL600V5-CS281I | IC FPGA 1KB FLASH 600K 281-CSP |
| AGL600V5-CSG281I | IC FPGA 1KB FLASH 600K 281-CSP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
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