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  • 參數(shù)資料
    型號(hào): A54SX32A-TQ100I
    廠商: Microsemi SoC
    文件頁(yè)數(shù): 1/108頁(yè)
    文件大?。?/td> 0K
    描述: IC FPGA SX 48K GATES 100-TQFP
    標(biāo)準(zhǔn)包裝: 90
    系列: SX-A
    LAB/CLB數(shù): 2880
    輸入/輸出數(shù): 81
    門(mén)數(shù): 48000
    電源電壓: 2.25 V ~ 5.25 V
    安裝類(lèi)型: 表面貼裝
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 100-LQFP
    供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
    February 2007
    i
    2007 Actel Corporation
    See the Actel website for the latest version of the datasheet.
    SX-A Family FPGAs
    Leading-Edge Performance
    250 MHz System Performance
    350 MHz Internal Performance
    Specifications
    12,000 to 108,000 Available System Gates
    Up to 360 User-Programmable I/O Pins
    Up to 2,012 Dedicated Flip-Flops
    0.22
    μ / 0.25 μ CMOS Process Technology
    Features
    Hot-Swap Compliant I/Os
    Power-Up/Down Friendly (No Sequencing Required
    for Supply Voltages)
    66 MHz PCI Compliant
    Nonvolatile, Single-Chip Solution
    Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
    TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
    2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
    5 V Input Tolerance and 5 V Drive Strength
    Devices Support Multiple Temperature Grades
    Configurable Weak-Resistor Pull-Up or Pull-Down
    for I/O at Power-Up
    Individual Output Slew Rate Control
    Up to 100% Resource Utilization and 100% Pin
    Locking
    Deterministic, User-Controllable Timing
    Unique In-System Diagnostic and Verification
    Capability with Silicon Explorer II
    Boundary-Scan Testing in Compliance with IEEE
    Standard 1149.1 (JTAG)
    Actel
    Secure
    Programming
    Technology
    with
    FuseLock Prevents Reverse Engineering and
    Design Theft
    e
    u
    Table 1 SX-A Product Profile
    Device
    A54SX08A
    A54SX16A
    A54SX32A
    A54SX72A
    Capacity
    Typical Gates
    System Gates
    8,000
    12,000
    16,000
    24,000
    32,000
    48,000
    72,000
    108,000
    Logic Modules
    Combinatorial Cells
    Dedicated Flip-Flops
    Maximum Flip-Flops
    768
    512
    256
    512 1
    1,452
    924
    528
    990
    2,880
    1,800
    1,080
    1,980
    6,036
    4,024
    2,012
    4,024
    Maximum User I/Os
    130
    180
    249
    360
    Global Clocks
    3
    Quadrant Clocks
    0
    4
    Boundary Scan Testing
    Yes
    3.3 V / 5 V PCI
    Yes
    Input Set-Up (External)
    0 ns
    Speed Grades2
    –F, Std, –1, –2
    –F, Std, –1, –2, –3
    Temperature Grades
    C, I, A, M
    Package (by pin count)
    PQFP
    TQFP
    PBGA
    FBGA
    CQFP
    208
    100, 144
    144
    208
    100, 144
    144, 256
    208
    100, 144, 176
    329
    144, 256, 484
    208, 256
    208
    256, 484
    208, 256
    Notes:
    1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers.
    2. All –3 speed grades have been discontinued.
    v5.3
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