鍨嬭櫉锛� | A54SX32A-BGG329I |
寤犲晢锛� | Microsemi SoC |
鏂囦欢闋佹暩(sh霉)锛� | 18/108闋� |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC FPGA SX 48K GATES 329-BGA |
妯欐簴鍖呰锛� | 27 |
绯诲垪锛� | SX-A |
LAB/CLB鏁�(sh霉)锛� | 2880 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 249 |
闁€鏁�(sh霉)锛� | 48000 |
闆绘簮闆诲锛� | 2.25 V ~ 5.25 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | -40°C ~ 85°C |
灏佽/澶栨锛� | 329-BBGA |
渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 329-PBGA锛�31x31锛� |
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
---|---|
A54SX32A-1BG329 | IC FPGA SX 48K GATES 329-BGA |
A54SX32A-BG329I | IC FPGA SX 48K GATES 329-BGA |
A54SX32A-1BGG329 | IC FPGA SX 48K GATES 329-BGA |
A54SX72A-FFG256 | IC FPGA SX-A 108K 256-FBGA |
A54SX72A-FFGG256 | IC FPGA SX-A 108K 256-FBGA |
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
---|---|
A54SX32A-BGG329M | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A Family 32K Gates 1800 Cells 238MHz 0.25um Technology 2.5V 329-Pin BGA 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A 32K GATES 1800 CELLS 238MHZ 0.25UM/0.22UM 2.5V 329 - Trays |
A54SX32A-CQ208 | 鍔熻兘鎻忚堪:IC FPGA SX 48K GATES 208-CQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳鍟嗚ō鍌欏皝瑁�:352-CQFP锛�75x75锛� |
A54SX32A-CQ208B | 鍔熻兘鎻忚堪:IC FPGA SX 48K GATES 208-CQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳鍟嗚ō鍌欏皝瑁�:352-CQFP锛�75x75锛� |
A54SX32A-CQ208M | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A Family 32K Gates 1800 Cells 238MHz 0.25um/0.22um (CMOS) Technology 2.5V 208-Pin CQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A 32K GATES 1800 CELLS 238MHZ 0.25UM/0.22UM 2.5V 208 - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 48K GATES 208CQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 174 I/O 208CQFP |
A54SX32A-CQ256 | 鍔熻兘鎻忚堪:IC FPGA SX 48K GATES 256-CQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳鍟嗚ō鍌欏皝瑁�:352-CQFP锛�75x75锛� |