Table 2-18 A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A54SX32A-1TQ100
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 47/108闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 48K GATES 100-TQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 2880
杓稿叆/杓稿嚭鏁�(sh霉)锛� 81
闁€鏁�(sh霉)锛� 48000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-LQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�鐣跺墠绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�
SX-A Family FPGAs
v5.3
2-23
Table 2-18 A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70掳C)
Parameter
Description
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
2.5 V LVCMOS Output Module Timing1,2
tDLH
Data-to-Pad Low to High
3.9
4.4
5.2
7.2
ns
tDHL
Data-to-Pad High to Low
3.0
3.4
3.9
5.5
ns
tDHLS
Data-to-Pad High to Low鈥攍ow slew
13.3
15.1
17.7
24.8
ns
tENZL
Enable-to-Pad, Z to L
2.8
3.2
3.7
5.2
ns
tENZLS
Data-to-Pad, Z to L鈥攍ow slew
13.7
15.5
18.2
25.5
ns
tENZH
Enable-to-Pad, Z to H
3.9
4.4
5.2
7.2
ns
tENLZ
Enable-to-Pad, L to Z
2.5
2.8
3.3
4.7
ns
tENHZ
Enable-to-Pad, H to Z
3.0
3.4
3.9
5.5
ns
dTLH
3
Delta Low to High
0.037
0.043
0.051
0.071
ns/pF
dTHL
3
Delta High to Low
0.017
0.023
0.037
ns/pF
dTHLS
3
Delta High to Low鈥攍ow slew
0.06
0.071
0.086
0.117
ns/pF
Note:
1. Delays based on 35 pF loading.
2. The equivalent I/O Attribute Editor settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI 鈥� 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
A54SX32A-1TQG100 IC FPGA SX 48K GATES 100-TQFP
A54SX32A-TQG100I IC FPGA SX 48K GATES 100-TQFP
EPF6024ABC256-1 IC FLEX 6000 FPGA 24K 256-BGA
AGL400V5-FGG256I IC FPGA 1KB FLASH 400K 256FBGA
ACC40DRYN-S93 CONN EDGECARD 80POS DIP .100 SLD
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
A54SX32A-1TQ100I 鍔熻兘鎻忚堪:IC FPGA SX 48K GATES 100-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX32A-1TQ100M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 100 - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 48K GATES 100TQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 81 I/O 100TQFP
A54SX32A-1TQ144 鍔熻兘鎻忚堪:IC FPGA SX 48K GATES 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX32A-1TQ144I 鍔熻兘鎻忚堪:IC FPGA SX 48K GATES 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX32A-1TQ144M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A Family 32K Gates 1800 Cells 278MHz 0.25um/0.22um (CMOS) Technology 2.5V 144-Pin TQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 144 - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 113 I/O 144TQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 48K GATES 144TQFP