Table 1-8 A54SX16P DC Specifications (3.3 V PCI Operation) Symbol " />
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寤犲晢锛� Microsemi SoC
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鏂囦欢澶�?銆�?/td> 0K
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� SX
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SX Family FPGAs
1- 12
v3.2
A54SX16P DC Specifications (3.3 V PCI Operation)
Table 1-8
A54SX16P DC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
VCCA
Supply Voltage for Array
3.0
3.6
V
VCCR
Supply Voltage required for Internal Biasing
3.0
3.6
V
VCCI
Supply Voltage for I/Os
3.0
3.6
V
VIH
Input High Voltage
0.5VCC
VCC + 0.5
V
VIL
Input Low Voltage
鈥�0.5
0.3VCC
V
IIPU
Input Pull-up Voltage1
0.7VCC
V
IIL
Input Leakage Current2
0 < VIN < VCC
卤10
A
VOH
Output High Voltage
IOUT = 鈥�500 A
0.9VCC
V
VOL
Output Low Voltage
IOUT = 1500 A
0.1VCC
V
CIN
Input Pin Capacitance3
10
pF
CCLK
CLK Pin Capacitance
5
12
pF
CIDSEL
IDSEL Pin Capacitance4
8pF
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a
floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current
at this input voltage.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A54SX16P-1VQG100I IC FPGA SX 24K GATES 100-VQFP
HMC49DREN-S734 CONN EDGECARD 98POS .100 EYELET
HMC49DREH-S734 CONN EDGECARD 98POS .100 EYELET
ABC44DRYI-S734 CONN EDGECARD 88POS DIP .100 SLD
RCB90DHAS CONN EDGECARD 180PS R/A .050 DIP
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