Table 1-19 A54SX16P Timing Characteristics (Worst-Case Commercial " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX16P-1TQ176I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 26/64闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA SX 24K GATES 176-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� SX
LAB/CLB鏁�(sh霉)锛� 1452
杓稿叆/杓稿嚭鏁�(sh霉)锛� 147
闁€(m茅n)鏁�(sh霉)锛� 24000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 176-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 176-TQFP锛�24x24锛�
SX Family FPGAs
1- 28
v3.2
A54SX16P Timing Characteristics
Table 1-19 A54SX16P Timing Characteristics
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70掳C)
Parameter
Description
'鈥�3' Speed
'鈥�2' Speed
'鈥�1' Speed
'Std' Speed
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
C-Cell Propagation Delays1
tPD
Internal Array Module
0.6
0.7
0.8
0.9
ns
Predicted Routing Delays2
tDC
FO = 1 Routing Delay, Direct Connect
0.1
ns
tFC
FO = 1 Routing Delay, Fast Connect
0.3
0.4
0.5
ns
tRD1
FO = 1 Routing Delay
0.3
0.4
0.5
ns
tRD2
FO = 2 Routing Delay
0.6
0.7
0.8
0.9
ns
tRD3
FO = 3 Routing Delay
0.8
0.9
1.0
1.2
ns
tRD4
FO = 4 Routing Delay
1.0
1.2
1.4
1.6
ns
tRD8
FO = 8 Routing Delay
1.9
2.2
2.5
2.9
ns
tRD12
FO = 12 Routing Delay
2.8
3.2
3.7
4.3
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.9
1.1
1.3
1.4
ns
tCLR
Asynchronous Clear-to-Q
0.5
0.6
0.7
0.8
ns
tPRESET
Asynchronous Preset-to-Q
0.7
0.8
0.9
1.0
ns
tSUD
Flip-Flop Data Input Set-Up
0.5
0.7
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
1.4
1.6
1.8
2.1
ns
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
1.5
1.7
1.9
2.2
ns
tINYL
Input Data Pad-to-Y LOW
1.5
1.7
1.9
2.2
ns
Predicted Input Routing Delays2
tIRD1
FO = 1 Routing Delay
0.3
0.4
0.5
ns
tIRD2
FO = 2 Routing Delay
0.6
0.7
0.8
0.9
ns
tIRD3
FO = 3 Routing Delay
0.8
0.9
1.0
1.2
ns
tIRD4
FO = 4 Routing Delay
1.0
1.2
1.4
1.6
ns
tIRD8
FO = 8 Routing Delay
1.9
2.2
2.5
2.9
ns
tIRD12
FO = 12 Routing Delay
2.8
3.2
3.7
4.3
ns
Note:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 10 pF loading.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
XM2S-2513 HOOD COVER 25POS FOR XM CONN
A54SX16P-2TQG176 IC FPGA SX 24K GATES 176-TQFP
XM2S-3713 HOOD COVER 37POS FOR XM CONN
A54SX16P-2TQ176 IC FPGA SX 24K GATES 176-TQFP
A54SX16P-1TQG176I IC FPGA SX 24K GATES 176-TQFP
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鍙冩暩(sh霉)鎻忚堪
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A54SX16P-1TQG176 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 176-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛� 绯诲垪:SX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€(m茅n)鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
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