Table 2-10 AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Min. Max. Units I
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寤犲晢锛� Microsemi SoC
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妯欐簴鍖呰锛� 160
绯诲垪锛� SX-A
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 111
闁€鏁�(sh霉)锛� 24000
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宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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SX-A Family FPGAs
2- 6
v5.3
Table 2-10 AC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT 鈮� 0.3VCCI
1
鈥�12VCCI
鈥搈A
0.3VCCI 鈮� VOUT < 0.9VCCI
1
(鈥�17.1(VCCI 鈥� VOUT))
鈥�
mA
0.7VCCI < VOUT < VCCI
1, 2
鈥�
鈥�
(Test Point)
VOUT = 0.7VCC
2
鈥撯€�32VCCI
mA
IOL(AC)
Switching Current Low
VCCI > VOUT 鈮� 0.6VCCI
1
16VCCI
鈥搈A
0.6VCCI > VOUT > 0.1VCCI
1
(26.7VOUT)鈥�
mA
0.18VCCI > VOUT > 0
1, 2
鈥�
鈥�
(Test Point)
VOUT = 0.18VCC
2
鈥�
38VCCI
mA
ICL
Low Clamp Current
鈥�3 < VIN 鈮� 鈥�1
鈥�25 + (VIN + 1)/0.015
鈥�
mA
ICH
High Clamp Current
VCCI + 4 > VIN 鈮� VCCI + 1
25 + (VIN 鈥� VCCI 鈥� 1)/0.015
鈥�
mA
slewR
Output Rise Slew Rate
0.2VCCI - 0.6VCCI load
3
14
V/ns
slewF
Output Fall Slew Rate
0.6VCCI - 0.2VCCI load
3
14
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. 鈥淪witching Current High鈥� specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
Output
Buffer
1/2 in. max.
10 pF
Pin
1 k/25
1 k/25
Pin
Buffer
Output
10 pF
鐩搁棞PDF璩囨枡
PDF鎻忚堪
GMC60DRYH-S93 CONN EDGECARD 120PS DIP .100 SLD
RBB85DHBT CONN EDGECARD 170PS R/A .050 DIP
ABB34DHBT CONN EDGECARD 68POS R/A .050 SLD
AMM25DRSI CONN EDGECARD 50POS DIP .156 SLD
RSM44DREN CONN EDGECARD 88POS .156 EYELET
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A54SX16A-FGG144M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A Family 16K Gates 924 Cells 227MHz 0.25um Technology 2.5V 144-Pin FBGA 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA SX-A 16K GATES 924 CELLS 227MHZ 0.25UM/0.22UM 2.5V 144F - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 111 I/O 144FBGA 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 24K GATES 144FBGA
A54SX16A-FGG256 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 256-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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