Table 2-23 A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A54SX16A-1FG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 53/108闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 24K GATES 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 1452
杓稿叆/杓稿嚭鏁�(sh霉)锛� 111
闁€鏁�(sh霉)锛� 24000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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SX-A Family FPGAs
v5.3
2-29
Table 2-23 A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70掳C)
Parameter
Description
鈥�3 Speed*
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.2
1.4
1.6
1.8
2.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.0
1.1
1.3
1.5
2.2
ns
tHPWH
Minimum Pulse Width High
1.4
1.7
1.9
2.2
3.0
ns
tHPWL
Minimum Pulse Width Low
1.4
1.7
1.9
2.2
3.0
ns
tHCKSW
Maximum Skew
0.3
0.4
0.6
ns
tHP
Minimum Period
2.8
3.4
3.8
4.4
6.0
ns
fHMAX
Maximum Frequency
357
294
263
227
167
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
1.0
1.2
1.3
1.5
2.1
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
1.1
1.3
1.5
1.7
2.4
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
1.1
1.3
1.4
1.7
2.3
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
1.1
1.3
1.5
1.7
2.4
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
1.3
1.5
1.7
2.0
2.7
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
1.3
1.5
1.7
2.0
2.8
ns
tRPWH
Minimum Pulse Width High
1.4
1.7
1.9
2.2
3.0
ns
tRPWL
Minimum Pulse Width Low
1.4
1.7
1.9
2.2
3.0
ns
tRCKSW
Maximum Skew (Light Load)
0.8
0.9
1.0
1.2
1.7
ns
tRCKSW
Maximum Skew (50% Load)
0.8
0.9
1.0
1.2
1.7
ns
tRCKSW
Maximum Skew (100% Load)
1.0
1.1
1.3
1.5
2.1
ns
Note: *All 鈥�3 speed grades have been discontinued.
鐩搁棞(gu膩n)PDF璩囨枡
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A54SX16A-1FG256 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 256-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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