Table 2-29 A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 81
闁€鏁�(sh霉)锛� 12000
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SX-A Family FPGAs
2- 36
v5.3
Table 2-29 A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70掳C)
Parameter
Description
鈥�3 Speed*
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tHPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tHCKSW
Maximum Skew
0.6
0.7
0.8
1.3
ns
tHP
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.5
2.9
3.4
4.7
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
2.1
2.4
2.7
3.2
4.4
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.1
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
2.2
2.5
2.8
3.3
4.6
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
2.5
2.9
3.2
3.8
5.3
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.0
ns
tRPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tRPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tRCKSW
Maximum Skew (Light Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (50% Load)
0.9
1.0
1.2
1.4
1.9
ns
tRCKSW
Maximum Skew (100% Load)
0.9
1.0
1.2
1.4
1.9
ns
Note: *All 鈥�3 speed grades have been discontinued.
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