Table 2-5 3.3 V LVTTL and 5 V TTL Electrical Specifications Symbol Parameter Commercial " />
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鍨嬭櫉(h脿o)锛� A54SX08A-PQ208I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 24/108闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 12K GATES 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 130
闁€鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)鐣�(d膩ng)鍓嶇24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)
SX-A Family FPGAs
2- 2
v5.3
Electrical Specifications
Table 2-5 3.3 V LVTTL and 5 V TTL Electrical Specifications
Symbol
Parameter
Commercial
Industrial
Min.
Max.
Min.
Max.
Units
VOH
VCCI = Minimum
VI = VIH or VIL
(IOH = 鈥�1 mA)
0.9 VCCI
V
VCCI = Minimum
VI = VIH or VIL
(IOH = 鈥�8 mA)
2.4
V
VOL
VCCI = Minimum
VI = VIH or VIL
(IOL= 1 mA)
0.4
V
VCCI = Minimum
VI = VIH or VIL
(IOL= 12 mA)
0.4
V
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
2.0
5.75
2.0
5.75
V
IIL/IIH
Input Leakage Current, VIN = VCCI or GND
鈥�10
10
鈥�10
10
A
IOZ
Tristate Output Leakage Current
鈥�10
10
鈥�10
10
A
tR, tF
Input Transition Time tR, tF
10
ns
CIO
I/O Capacitance
10
pF
ICC
Standby Current
10
20
mA
IV Curve* Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.
Table 2-6 2.5 V LVCMOS2 Electrical Specifications
Symbol
Parameter
Commercial
Industrial
Min.
Max.
Min.
Max.
Units
VOH
VDD = MIN,
VI = VIH or VIL
(IOH = 鈥�100 渭A)
2.1
V
VDD = MIN,
VI = VIH or VIL
(IOH = 鈥�1 mA)
2.0
V
VDD = MIN,
VI = VIH or VIL
(IOH =鈥�-2 mA)
1.7
V
VOL
VDD = MIN,
VI = VIH or VIL
(IOL= 100 渭A)
0.2
V
VDD = MIN,
VI = VIH or VIL
(IOL= 1 mA)
0.4
V
VDD = MIN,
VI = VIH or VIL
(IOL= 2 mA)
0.7
V
VIL
Input Low Voltage, VOUT 鈮� VVOL(max)
-0.3
0.7
-0.3
0.7
V
VIH
Input High Voltage, VOUT 鈮� VVOH(min)
1.75.751.7
5.75
V
IIL/IIH
Input Leakage Current, VIN = VCCI or GND
鈥�10
10
鈥�10
10
A
IOZ
Tristate Output Leakage Current, VOUT = VCCI or GND
鈥�10
10
鈥�10
10
A
tR, tF
Input Transition Time tR, tF
10
ns
CIO
I/O Capacitance
10
pF
ICC
Standby Current
10
20
mA
IV Curve* Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.
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A54SX08A-PQ208M 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:SX-A Family FPGAs
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A54SX08APQG208A 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:SX-A Family FPGAs
A54SX08A-PQG208A 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 208-PQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:SX-A 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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