Table 2-20 A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX08A-2TQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 49/108闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA SX 12K GATES 100-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 81
闁€鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)鐣�(d膩ng)鍓嶇49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)
SX-A Family FPGAs
v5.3
2-25
Table 2-20 A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70掳C)
Parameter
Description
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
5 V PCI Output Module Timing1
tDLH
Data-to-Pad Low to High
2.4
2.8
3.2
4.5
ns
tDHL
Data-to-Pad High to Low
3.2
3.6
4.2
5.9
ns
tENZL
Enable-to-Pad, Z to L
1.5
1.7
2.0
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.4
2.8
3.2
4.5
ns
tENLZ
Enable-to-Pad, L to Z
3.5
3.9
4.6
6.4
ns
tENHZ
Enable-to-Pad, H to Z
3.2
3.6
4.2
5.9
ns
dTLH
2
Delta Low to High
0.016
0.02
0.022
0.032
ns/pF
dTHL
2
Delta High to Low
0.03
0.032
0.04
0.052
ns/pF
5 V TTL Output Module Timing3
tDLH
Data-to-Pad Low to High
2.4
2.8
3.2
4.5
ns
tDHL
Data-to-Pad High to Low
3.2
3.6
4.2
5.9
ns
tDHLS
Data-to-Pad High to Low鈥攍ow slew
7.6
8.6
10.1
14.2
ns
tENZL
Enable-to-Pad, Z to L
2.4
2.7
3.2
4.5
ns
tENZLS
Enable-to-Pad, Z to L鈥攍ow slew
8.4
9.5
11.0
15.4
ns
tENZH
Enable-to-Pad, Z to H
2.4
2.8
3.2
4.5
ns
tENLZ
Enable-to-Pad, L to Z
4.2
4.7
5.6
7.8
ns
tENHZ
Enable-to-Pad, H to Z
3.2
3.6
4.2
5.9
ns
dTLH
Delta Low to High
0.017
0.023
0.031
ns/pF
dTHL
Delta High to Low
0.029
0.031
0.037
0.051
ns/pF
dTHLS
Delta High to Low鈥攍ow slew
0.046
0.057
0.066
0.089
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI 鈥� 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
3. Delays based on 35 pF loading.
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