Table 2-10 AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Min. Max. Units I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX08A-2TQ144
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 28/108闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 12K GATES 144-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 113
闁€鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)鐣�(d膩ng)鍓嶇28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)
SX-A Family FPGAs
2- 6
v5.3
Table 2-10 AC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT 鈮� 0.3VCCI
1
鈥�12VCCI
鈥搈A
0.3VCCI 鈮� VOUT < 0.9VCCI
1
(鈥�17.1(VCCI 鈥� VOUT))
鈥�
mA
0.7VCCI < VOUT < VCCI
1, 2
鈥�
鈥�
(Test Point)
VOUT = 0.7VCC
2
鈥撯€�32VCCI
mA
IOL(AC)
Switching Current Low
VCCI > VOUT 鈮� 0.6VCCI
1
16VCCI
鈥搈A
0.6VCCI > VOUT > 0.1VCCI
1
(26.7VOUT)鈥�
mA
0.18VCCI > VOUT > 0
1, 2
鈥�
鈥�
(Test Point)
VOUT = 0.18VCC
2
鈥�
38VCCI
mA
ICL
Low Clamp Current
鈥�3 < VIN 鈮� 鈥�1
鈥�25 + (VIN + 1)/0.015
鈥�
mA
ICH
High Clamp Current
VCCI + 4 > VIN 鈮� VCCI + 1
25 + (VIN 鈥� VCCI 鈥� 1)/0.015
鈥�
mA
slewR
Output Rise Slew Rate
0.2VCCI - 0.6VCCI load
3
14
V/ns
slewF
Output Fall Slew Rate
0.6VCCI - 0.2VCCI load
3
14
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. 鈥淪witching Current High鈥� specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
Output
Buffer
1/2 in. max.
10 pF
Pin
1 k/25
1 k/25
Pin
Buffer
Output
10 pF
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ABM43DTMH-S189 CONN EDGECARD 86POS R/A .156 SLD
A54SX08A-1TQG144I IC FPGA SX 12K GATES 144-TQFP
ACM44DSES-S243 CONN EDGECARD 88POS .156 EYELET
A54SX08A-2TQG144 IC FPGA SX 12K GATES 144-TQFP
A54SX08A-1TQ144I IC FPGA SX 12K GATES 144-TQFP
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A54SX08A-2TQ144I 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:SX-A 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A54SX08A-2TQ208 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:SX-A Family FPGAs
A54SX08A-2TQ208A 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:SX-A Family FPGAs
A54SX08A-2TQ208B 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:SX-A Family FPGAs
A54SX08A-2TQ208I 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:SX-A Family FPGAs