Table 2-31 A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A54SX08A-2FGG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 63/108闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 12K GATES 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 111
闁€鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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SX-A Family FPGAs
2- 38
v5.3
Table 2-31 A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70掳C)
Parameter
Description
鈥�3 Speed*
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
1.9
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tHPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tHCKSW
Maximum Skew
0.6
0.7
0.8
1.3
ns
tHP
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.5
2.8
3.3
4.7
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
2.1
2.5
2.8
3.3
4.5
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.1
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
2.2
2.6
2.9
3.4
4.7
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
2.5
2.8
3.2
3.8
5.3
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.4
2.8
3.1
3.7
5.2
ns
tRPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tRPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tRCKSW
Maximum Skew (Light Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (50% Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (100% Load)
1.0
1.1
1.3
1.5
2.1
ns
Note: *All 鈥�3 speed grades have been discontinued.
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