External Setup = tINY + t
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX08-VQ100
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 18/64闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 12K GATES 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� SX
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 81
闁€(m茅n)鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
SX Family FPGAs
v3.2
1-21
SX Timing Model
Hardwired Clock
External Setup = tINY + tIRD1 + tSUD 鈥� tHCKH
= 1.5 + 0.3 + 0.5 鈥� 1.0 = 1.3 ns
EQ 1-15
Clock-to-Out (Pin-to-Pin)
=tHCKH + tRCO + tRD1 + tDHL
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns
EQ 1-16
Routed Clock
External Setup = tINY + tIRD1 + tSUD 鈥� tRCKH
= 1.5 + 0.3 + 0.5 鈥� 1.5 = 0.8 ns
EQ 1-17
Clock-to-Out (Pin-to-Pin)
=tRCKH + tRCO + tRD1 + tDHL
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns
EQ 1-18
Note: Values shown for A54SX08-3, worst-case commercial conditions.
Figure 1-12 SX Timing Model
DQ
Routed
Clock
F
MAX = 250 MHz
t
RCKH = 1.5 ns (100% Load)
t
INY = 1.5 ns
Output Delays
Input Delays
I/O Module
Combinatorial Cell
Register Cell
I/O Module
Hardwired
Clock
DQ
Predicted
Routing
Delays
t
IRD2 = 0.6 ns
t
PD = 0.6 ns
t
RD1 = 0.3 ns
t
RD4 = 1.0 ns
t
RD8 = 1.9 ns
t
DLH = 1.6 ns
t
DHL = 1.6 ns
F
HMAX = 320 MHz
t
HCKH = 1.0 ns
t
RCO = 0.8 ns
t
RD1 = 0.3 ns
t
ENZH = 2.3 ns
Internal Delays
t
RD1 = 0.3 ns
t
SUD = 0.5 ns
t
HD = 0.0 ns
Register Cell
t
RCO = 0.8 ns
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A54SX08-VQ100I 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 100-VQFP RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:SX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€(m茅n)鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX08-VQ100M 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū(ch膿ng):鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA)
A54SX08-VQ208 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū(ch膿ng):鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs
A54SX08-VQ208I 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū(ch膿ng):鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs
A54SX08-VQ208M 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū(ch膿ng):鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs