參數(shù)資料
型號(hào)： A54SX08-PLG84I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 20/64頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 84-PLCC
標(biāo)準(zhǔn)包裝： 16
系列： SX
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 69
門數(shù)： 12000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.31x29.31）
SX Family FPGAs
v3.2
1-23
Register Cell Timing Characteristics
Timing Characteristics
Timing characteristics for SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
The
input
and
output
buffer
characteristics are common to all SX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design is
complete. Delay values may then be determined by using
the DirectTime Analyzer utility or performing simulation
with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most time-
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6% of the nets in a design may be designated as
critical, while 90% of the nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes five antifuse connections. This increases
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically up to 6
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to 8.4
ns delay. This additional delay is represented statistically
in higher fanout (FO = 24) routing delays in the
datasheet specifications section.
Timing Derating
SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum
operating
temperature,
and
best-case
processing.
Maximum
timing
parameters
reflect
minimum
operating
voltage,
maximum
operating
temperature, and worst-case processing.
Figure 1-17 Flip-Flops
t
CLR
(positive edge triggered)
D
CLK
CLR
PRESET
Q
D
CLK
Q
CLR
PRESET
t
HPWH'
t
WASYN
t
HD
t
SUD
t
HP
t
HPWL
'
t
RCO
t
PRESET
RPWL
RPWH
相關(guān)PDF資料
PDF描述
A54SX08-PL84I IC FPGA SX 12K GATES 84-PLCC
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