參數(shù)資料
型號： A54SX08-2VQG100I
廠商： Microsemi SoC
文件頁數(shù)： 56/64頁
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 100-VQFP
標準包裝： 90
系列： SX
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 81
門數(shù)： 12000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應商設備封裝： 100-VQFP（14x14）
SX Family FPGAs
1- 2
v3.2
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-2). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility
while
allowing
mapping
of
synthesized
functions into the SX FPGA. The clock source for the
R-cell can be chosen from either the hardwired clock or
the routed clock.
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 1-3 on page 1-3). Inclusion of the
DB input and its associated inverter function dramatically
increases the number of combinatorial functions that can
be implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to
integrate a 3-input exclusive-OR function into a single
C-cell. This facilitates construction of 9-bit parity-tree
functions with 2 ns propagation delays. At the same
time, the C-cell structure is extremely synthesis friendly,
simplifying the overall design and reducing synthesis
time.
Figure 1-1
SX Family Interconnect Elements
Figure 1-2
R-Cell
Silicon Substrate
Tungsten Plug
Contact
Metal 1
Metal 2
Metal 3
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Direct
Connect
Input
CLKA, CLKB,
Internal Logic
HCLK
CKS
CKP
CLRB
PSETB
Y
DQ
Routed Data Input
S0
S1
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