VCCA U4 I/O U20 I/O U21 " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX08-1TQG176
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 57/64闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 12K GATES 176-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� SX
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 128
闁€鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 176-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 176-TQFP锛�24x24锛�
54SX Family FPGAs
2- 22
v3.2
T22
I/O
T23
I/O
U1
I/O
U2
I/O
U3
VCCA
U4
I/O
U20
I/O
U21
VCCA
U22
I/O
U23
I/O
V1
VCCI
V2
I/O
V3
I/O
329-Pin PBGA
Pin
Number
A54SX32
Function
V4
I/O
V20
I/O
V21
I/O
V22
I/O
V23
I/O
W1
I/O
W2
I/O
W3
I/O
W4
I/O
W20
I/O
W21
I/O
W22
I/O
329-Pin PBGA
Pin
Number
A54SX32
Function
W23
NC
Y1
NC
Y2
I/O
Y3
I/O
Y4
GND
Y5
I/O
Y6
I/O
Y7
I/O
Y8
I/O
Y9
I/O
Y10
I/O
Y11
I/O
329-Pin PBGA
Pin
Number
A54SX32
Function
Y12
VCCA
Y13
VCCR
Y14
I/O
Y15
I/O
Y16
I/O
Y17
I/O
Y18
I/O
Y19
I/O
Y20
GND
Y21
I/O
Y22
I/O
Y23
I/O
329-Pin PBGA
Pin
Number
A54SX32
Function
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
AMM22DTMH CONN EDGECARD 44POS R/A .156 SLD
EP4CGX30CF23C7 IC CYCLONE IV GX FPGA 30K 484FBG
AMM22DTMD CONN EDGECARD 44POS R/A .156 SLD
8655MH2511LF BACKSHELL DB25 STR METAL SHLD
3357-6250-1C CONN D-SUB SHELL 50POS PLASTIC
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A54SX08-1TQG176I 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 176-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:SX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX08-1VQ100 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:SX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX08-1VQ100I 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:SX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A54SX08-1VQ100M 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA)
A54SX08-1VQ208 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�(h脿o)锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

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    • 閲囪喘
    • 鎼滅储
    • 浼氬憳