參數(shù)資料
型號(hào)： A49LF004
廠商： AMIC Technology Corporation
英文描述： 4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
中文描述： 4兆位的CMOS 3.3Volt只閃存固件集線器
文件頁(yè)數(shù)： 7/32頁(yè)
文件大?。?/td> 595K
代理商： A49LF004
Table 2: FWH Read Cycle
A49LF004
PRELIMINARY (November, 2003, Version 0.0)
6
AMIC Technology, Corp.
FWH Single-Byte Read Waveforms
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
START
IDSEL
IMADDR
IMSIZE
TAR0
TAR1
RSYNC
DATA
TAR0
TAR1
FWH4
FWH[3:0]
Clock
Cycle
Field
FWH[3:0]
MEMORY
I/O
Descriptions
1
START
1101
IN
FWH4 must be active (low) for the part to respond. Only the last
start field (before FWH4 transitioning high) should be
recognized. The START field contents indicate an FWH read
cycle.
2
IDSEL
0000 to 1111
IN
Indicates which FWH device should respond. If the IDSEL (ID
select) field matches the value ID[3:0], then that particular device
will respond to subsequent commands.
3-9
IMADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are
transferred most-significant nibble first.
10
IMSIZE
0000 (1 byte)
IN
A field of this size indicates how many bytes will be transferred
during multibyte operations.
11
TAR0
1111
IN
then float
In this clock cycle, the master (Intel ICH) has driven the bus to all
1s and then floats the bus, prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float
then OUT
The FWH takes control of the bus during this cycle. During the
next clock cycle, it will be driven “sync data.”
13
RSYNC
0000 (READY)
OUT
During this clock cycle, the FWH will generate a “ready-sync”
(RSYNC) indicating that the least-significant nibble of the least-
significant byte will be available during the next clock cycle.
14
DATA
YYYY
OUT
YYYY is the least-significant nibble of the data byte.
15
DATA
YYYY
OUT
YYYY is the most-significant nibble of the data byte.
16
TAR0
1111
OUT
then float
In this clock cycle, the A49LF004 has driven the bus to all 1s and
then floats the bus prior to the next clock cycle. This is the first
part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float
then IN
The master (Intel ICH) resumes control of the bus during this
cycle.
相關(guān)PDF資料
PDF描述
A49LF040A 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040ATL-33 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040ATL-33F 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040ATX-33 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040ATX-33F 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A49LF004TL-33C 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
A49LF004TX-33C 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
A49LF040 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040A 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040ATL-33 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
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