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參數(shù)資料
| 型號(hào)： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 42/71頁(yè) |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
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A48P4616
Preliminary (September, 2005, Version 0.0)
41
AMIC Technology, Corp.
Power Down
Power Down is entered when CKE is registered low (no
accesses can be in progress). If Power Down occurs when
all banks are idle, this mode is referred to as Precharge
Power Down; if Power Down occurs when there is a row
active in any bank, this mode is referred to as Active Power
Down. Entering Power Down deactivates the input and
output buffers, excluding CK, CK and CKE. The DLL is still
running in Power Down mode, so for maximum power
savings, the user has the option of disabling the DLL prior to
entering Power Down. In that case, the DLL must be enabled
after exiting Power Down, and 200 clock cycles must occur
before a Read command can be issued.
In Power Down mode, CKE Low and a stable clock signal
must be maintained at the inputs of the DDR SDRAM, and all
other input signals are “Don’t Care”. However, Power Down
duration is limited by the refresh requirements of the device,
so in most applications, the self refresh mode is preferred
over the DLL-disabled Power Down mode.
The Power Down state is synchronously exited when CKE is
registered high (along with a Nop or Deselect command). A
valid, executable command may be applied one clock cycle
later.
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