參數(shù)資料
型號(hào): A43L4616
廠商: AMIC Technology Corporation
英文描述: 4M X 16 Bit X 4 Banks Synchronous DRAM
中文描述: 4米× 16位× 4個(gè)銀行同步DRAM
文件頁(yè)數(shù): 21/41頁(yè)
文件大?。?/td> 1063K
代理商: A43L4616
A43L4616
(September, 2004, Version 0.0)
20
AMIC Technology, Corp.
12. About Burst Type Control
Sequential counting
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
Basic
MODE
Interleave counting
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
Random
MODE
Random column Access
t
CCD
= 1 CLK
13. About Burst Length Control
1
At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
2
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = “010”
Basic
MODE
8
At MRS A2,1,0 = “011”.
At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
t
RDL
=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
Special
MODE
BRSW
RASInterrupt
(Interrupted by Precharge)
During read/write burst with auto precharge, RASinterrupt cannot be issued.
Interrupt
MODE
CAS
Interrupt
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge,
CAS
interrupt can not be issued.
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