參數(shù)資料
型號(hào): A43L3616V-7V
廠商: AMIC Technology Corporation
英文描述: 2M X 16 Bit X 4 Banks Synchronous DRAM
中文描述: 200萬× 16位× 4個(gè)銀行同步DRAM
文件頁數(shù): 8/41頁
文件大?。?/td> 865K
代理商: A43L3616V-7V
A43L3616
(February, 2002, Version 3.0)
8
AMIC Technology, Inc.
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol
Parameter
CAS Latency
-6
-7
Unit
Note
t
RRD(min)
Row active to row active delay
12
14
ns
1
t
RCD(min)
RAS to
CAS
delay
18
20
ns
1
t
RP(min)
Row precharge time
18
20
ns
1
t
RAS(min)
42
45
ns
1
t
RAS(max)
Row active time
100
μ
s
t
RC(min)
Row cycle time
60
63
ns
1
t
CDL(min)
Last data in new col. Address delay
6
7
ns
2
t
RDL(min)
Last data in row precharge
12
14
ns
2
t
BDL(min)
Last data in to burst stop
6
7
ns
2
t
CCD(min)
Col. Address to col. Address delay
3
6
7
ns
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
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