參數(shù)資料
型號: A43L2632V-7
廠商: AMIC Technology Corporation
英文描述: 1M X 32 Bit X 4 Banks Synchronous DRAM
中文描述: 100萬× 32位× 4個銀行同步DRAM
文件頁數(shù): 10/43頁
文件大?。?/td> 1072K
代理商: A43L2632V-7
A43L2632
PRELIMINARY
(January, 2005, Version 0.0)
9
AMIC Technology, Corp.
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol
Parameter
-6
-7
Unit
Note
t
RRD(min)
Row active to row active delay
12
15
ns
1
t
RCD(min)
RAS to
CAS
delay
15
15
ns
1
t
RP(min)
Row precharge time
15
15
ns
1
t
RAS(min)
42
42
ns
1
t
RAS(max)
Row active time
100
μ
s
t
RC(min)
Row cycle time
63
65
ns
1
t
CDL(min)
Last data in new col. Address delay
6
7
ns
2
t
RDL(min)
Last data in row precharge
12
14
ns
2
t
BDL(min)
Last data in to burst stop
6
7
ns
2
t
CCD(min)
Col. Address to col. Address delay
1
1
ns
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
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