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參數(shù)資料
| 型號： | A43L2632 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 1M X 32 Bit X 4 Banks Synchronous DRAM |
| 中文描述： | 100萬× 32位× 4個銀行同步DRAM |
| 文件頁數(shù)： | 7/43頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | A43L2632 |
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A43L2632
PRELIMINARY
(January, 2005, Version 0.0)
6
AMIC Technology, Corp.
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
C
DC1
0.1 + 0.01
μ
F
Decoupling Capacitance between VDDQ and VSSQ
C
DC2
0.1 + 0.01
μ
F
Note:
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C or T
A
= -40oC to +85oC )
Speed
Symbol
Parameter
Test Conditions
-6
-7
Unit
Notes
I
cc1
Operating Current
(One Bank Active)
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min
)
, I
OL
= 0mA
85
80
mA
1
I
cc2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
45
40
I
cc2
PS
Precharge Standby Current
in power-down mode
CKL
≤
VIL(max), t
CC
=
∞
3
3
mA
I
CC2
N
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during
30ns
8
I
CC2
NS
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable.
1
mA
I
CC3
N
Active Standby current in
non power-down mode
(One Bank Active)
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during
30ns
65
60
mA
I
CC4
Operating Current
(Burst Mode)
I
OL
= 0mA, Page Burst
All bank Activated, t
CCD
= t
CCD
(min)
200
170
mA
1
I
CC5
Refresh Current
t
RC
≥
t
RC
(min)
180
170
mA
2
I
CC6
Self Refresh Current
CKE = 0.2V
3
3
mA
Note:
1. Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2. Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
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