- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4413 > A42MX24-TQG176I (Microsemi SoC)IC FPGA MX SGL CHIP 36K 176-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | A42MX24-TQG176I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 52/142頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA MX SGL CHIP 36K 176-TQFP |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MX |
| 輸入/輸出數(shù)： | 150 |
| 門數(shù)： | 36000 |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-TQFP（24x24） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 13
Design Consideration
It is recommended to use a series 70
Ω termination resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70
Ω series termination is used to prevent data transmission corruption
during probing and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint
Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms
for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP
(test access port), TAP controller, test data registers and instruction register (Figure 1-13 on page 1-14).
This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and
BYPASS) and some optional instructions. Table 1-3 on page 1-14 describes the ports that control JTAG
testing, while Table 1-4 on page 1-14 describes the test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input),
TDI and TDO (test data input and output), and TMS (test mode selector).
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be
present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the
instruction register or the data register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for
five TCK cycles.
42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification,
and boundary scan. The bypass register is selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices in a test data path. The 32-bit device
identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part
number and version). The boundary-scan register observes and controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and
parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a
device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The
Table 1-2
Device Configuration Options for Probe Capability
Security Fuse(s)
Programmed
Mode
PRA, PRB1
SDI, SDO, DCLK1
No
LOW
User I/Os2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are
active during probing, input signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin
Descriptions" section on page 1-83 for information on unused I/O pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX32A-2FG484 | IC FPGA SX 48K GATES 484-FBGA |
| A54SX32A-1FG484I | IC FPGA SX 48K GATES 484-FBGA |
| A54SX32A-1FGG484I | IC FPGA SX 48K GATES 484-FBGA |
| A54SX32A-2FGG484 | IC FPGA SX 48K GATES 484-FBGA |
| EPF10K30RI208-4 | IC FLEX 10K FPGA 30K 208-RQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-TQG176M | 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 36K Gates 912 Cells 0.45um Technology 3.3V/5V 176-Pin TQFP 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 176TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP |
| A42MX36-1BG272 | 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX36-1BG272I | 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A42MX36-1BG272M | 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 90MHz/151MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 90MHZ/151MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA |
| A42MX36-1BGG272 | 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。