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  • 參數(shù)資料
    型號: A42MX16-PQG208I
    廠商: Microsemi SoC
    文件頁數(shù): 126/142頁
    文件大?。?/td> 0K
    描述: IC FPGA MX SGL CHIP 24K 208-PQFP
    標(biāo)準(zhǔn)包裝: 24
    系列: MX
    輸入/輸出數(shù): 140
    門數(shù): 24000
    電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 208-BFQFP
    供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
    40MX and 42MX FPGA Families
    1- 80
    R e v i sio n 1 1
    Synchronous SRAM Operations (continued)
    tADH
    Address/Data Hold Time
    0.0
    ns
    tRENSU
    Read Enable Set-Up
    0.9
    1.0
    1.1
    1.3
    1.8
    ns
    tRENH
    Read Enable Hold
    4.8
    5.3
    6.0
    7.0
    9.8
    ns
    tWENSU
    Write Enable Set-Up
    3.8
    4.2
    4.8
    5.6
    7.8
    ns
    tWENH
    Write Enable Hold
    0.0
    ns
    tBENS
    Block Enable Set-Up
    3.9
    4.3
    4.9
    5.7
    8.0
    ns
    tBENH
    Block Enable Hold
    0.0
    ns
    Asynchronous SRAM Operations
    tRPD
    Asynchronous Access Time
    11.3
    12.6
    14.3
    16.8
    23.5
    ns
    tRDADV
    Read Address Valid
    12.3
    13.7
    15.5
    18.2
    25.5
    ns
    tADSU
    Address/Data Set-Up Time
    2.3
    2.5
    2.8
    3.4
    4.8
    ns
    tADH
    Address/Data Hold Time
    0.0
    ns
    tRENSUA
    Read Enable Set-Up to Address
    Valid
    0.9
    1.0
    1.1
    1.3
    1.8
    ns
    tRENHA
    Read Enable Hold
    4.8
    5.3
    6.0
    7.0
    9.8
    ns
    tWENSU
    Write Enable Set-Up
    3.8
    4.2
    4.8
    5.6
    7.8
    ns
    tWENH
    Write Enable Hold
    0.0
    ns
    tDOH
    Data Out Hold Time
    1.8
    2.0
    2.1
    2.5
    3.5
    ns
    Input Module Propagation Delays
    tINPY
    Input Data Pad-to-Y
    1.4
    1.6
    1.8
    2.1
    3.0
    ns
    tINGO
    Input Latch Gate-to-Output
    2.0
    2.2
    2.5
    2.9
    4.1
    ns
    tINH
    Input Latch Hold
    0.0
    ns
    tINSU
    Input Latch Set-Up
    0.7
    0.8
    1.0
    1.4
    ns
    tILA
    Latch Active Pulse Width
    6.5
    7.3
    8.2
    9.7
    13.5
    ns
    Table 1-39 A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
    (Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
    –3 Speed
    –2 Speed
    –1 Speed
    Std Speed –F Speed
    Parameter / Description
    Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
    Notes:
    1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
    2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
    estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
    3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
    can be obtained from the Timer utility.
    4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
    External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
    external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
    5. Delays based on 35 pF loading.
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