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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | A42MX16-PQ100 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 91/142闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA MX SGL CHIP 24K 100-PQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 66 |
| 绯诲垪锛� | MX |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 83 |
| 闁€鏁�(sh霉)锛� | 24000 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 100-BQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-PQFP锛�14x20锛� |
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40MX and 42MX FPGA Families
1- 48
R e v i sio n 1 1
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.03
0.04
ns/pF
Table 1-30 A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70掳C)
鈥�3 Speed
鈥�2 Speed
鈥�1 Speed
Std Speed
鈥揊 Speed
Units
Parameter / Description
Min. Max.
Min.
Max. Min. Max. Min. Max. Min. Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| HCC65DRYI | CONN EDGECARD 130PS DIP .100 SLD |
| ESC30DTEF | CONN EDGECARD 60POS .100 EYELET |
| ACC43DRYI | CONN EDGECARD 86POS .100 DIP SLD |
| ACB80DHNN | CONN EDGECARD 160PS .050 DIP SLD |
| A42MX09-TQ176 | IC FPGA MX SGL CHIP 14K 176-TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A42MX16-PQ100A | 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 24K 100-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| A42MX16-PQ100ES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:40MX and 42MX FPGA Families |
| A42MX16-PQ100I | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 42MX Family 24K Gates 608 Cells 103MHz/172MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 24K GATES 608 CELLS 103MHZ/172MHZ 0.45UM 3.3V/5V 100PQF - Trays |
| A42MX16-PQ100M | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 42MX Family 24K Gates 608 Cells 103MHz/172MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 24K GATES 608 CELLS 103MHZ/172MHZ 0.45UM 3.3V/5V 100PQF - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 24K 100-PQFP |
| A42MX16-PQ160 | 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 24K 160-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
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