- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375137 > A418316V-35U (AMIC Technology Corporation) 256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE PDF資料下載
參數(shù)資料
| 型號： | A418316V-35U |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| 中文描述： | 256 × 16的CMOS動態(tài)RAM的快速頁面模式 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 278K |
| 代理商： | A418316V-35U |
A418316 Series
PRELIMINARY
(July, 2003,Version 0.0)
2
AMIC Technology, Inc.
Selection Guide
Symbol
Description
-25
-35
Unit
t
RAC
Maximum RAS Access Time
25
35
ns
t
AA
Maximum Column Address Access Time
12
17
ns
t
CAC
Maximum CAS Access Time
8
10
ns
t
OEA
Maximum Output Enable (OE) Access Time
8
10
ns
t
RC
Minimum Read or Write Cycle Time
44
62
ns
t
PC
Minimum FAST Cycle Time
15
19
ns
Functional Description
The A418316 reads and writes data by multiplexing an 18-
bit address into a 9-bit row and 9-bit column address.
RAS
and
CAS
are used to strobe the row address and the
column address, respectively.
The A418316 has two
CAS
inputs:
LCAS
controls I/O
0
-
I/O
7
, and
UCAS
controls I/O
8
-
I/O
15
,
UCAS
and
LCAS
function in an identical manner to
CAS
in that either will
generate an internal
CAS
signal. The
CAS
function and
timing are determined by the first
CAS
(
UCAS
or
LCAS
) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using
LCAS
and
UCAS
separately.
A Read cycle is performed by holding the WE signal high
during RAS/
CAS
operation. A Write cycle is executed by
holding the WE signal low during RAS /
CAS
operation;
the input data is latched by the falling edge of WE or
CAS
, whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS,
CAS
,
WE and OE controlling the in direction.
FAST Page Mode operation all 512 columns within a
selected row to be randomly accessed at a high data rate.
A FAST Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS
. While holding RAS low,
CAS
can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A418316 offers an accelerated Fast Page Mode cycle.
A memory cycle is terminated by returning both RAS and
CAS
high. Memory cell data will retain its correct state by
maintaining power and accessing all 512 combinations of
the 9-bit row addresses, regardless of sequence, at least
once every 8ms through any RAS cycle (Read, Write) or
RAS Refresh cycle (RAS-only, CBR, or Hidden). The CBR
Refresh cycle automatically controls the row addresses by
invoking the refresh counter and controller.
Power-On
The initial application of the VCC supply requires a 200 μs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and
CAS
.
It is recommended that RAS and
CAS
track with VCC or
be held at a valid V
IH
during Power-On to avoid current
surges.
相關PDF資料 |
PDF描述 |
|---|---|
| A418316S | 256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| A418316 | 256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| A418316V | 256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| A420616 | 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
| A420616S-45 | 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A4184-02 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:Housings, Power and Signal Cables, Connector Adapters |
| A4184-03 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:Housings, Power and Signal Cables, Connector Adapters |
| A-418A | 制造商:DWYER INSTRUMENTS 功能描述:A-418A ASSY PRESS SNSR WALL MT |
| A419-063394-03 | 制造商:Guardian Electric Manufacturing 功能描述: |
| A-419A | 制造商:DWYER INSTRUMENTS 功能描述:A-419A PR SNSR CLG MT ASSY |
發(fā)布緊急采購，3分鐘左右您將得到回復。