(Normalized to T" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A40MX04-2PLG44I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 80/142闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA MX SGL CHIP 6K 44-PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 27
绯诲垪锛� MX
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€鏁�(sh霉)锛� 6000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 44-PLCC锛�16.59x16.59锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�鐣�(d膩ng)鍓嶇80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�
40MX and 42MX FPGA Families
1- 38
R e v i sio n 1 1
Table 1-25 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25掳C, VCC = 3.3 V)
40MX Voltage
Temperature
鈥�55掳C
鈥�40掳C
0掳C
25掳C
70掳C
85掳C
125掳C
3.00
1.08
1.12
1.21
1.26
1.50
1.64
2.00
3.30
0.86
0.89
0.96
1.00
1.19
1.30
1.59
3.60
0.83
0.85
0.92
0.96
1.14
1.25
1.53
Note:
This derating factor applies to all routing and propagation delays.
Figure 1-36 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25掳C, VCC = 3.3 V)
3.00
3.30
3.60
Voltage (V)
g
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
55C
40C
0C
25C
70C
85C
125C
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A40MX04-2PL44I IC FPGA MX SGL CHIP 6K 44-PLCC
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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