tSTG Storage Temperature 鈥�65 to +150 掳C Note: *Stres" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A40MX02-PL68I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 57/142闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA MX SGL CHIP 3K 68-PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 19
绯诲垪锛� MX
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 3000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 68-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 68-PLCC锛�24.23x24.23锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�鐣�(d膩ng)鍓嶇57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 17
tSTG
Storage Temperature
鈥�65 to +150
掳C
Note:
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-7
Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
鈥�0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
鈥�0.5 to +7.0
V
VI
Input Voltage
鈥�0.5 to VCCI+0.5
V
VO
Output Voltage
鈥�0.5 to VCCI+0.5
V
tSTG
Storage Temperature
鈥�65 to +150
掳C
Note:
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-8
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
鈥�40 to +85
鈥�55 to +125
掳C
VCC (40MX)
4.75 to 5.25
4.5 to 5.5
V
VCCA (42MX)
4.75 to 5.25
4.5 to 5.5
V
VCCI (42MX)
4.75 to 5.25
4.5 to 5.5
V
Note:
*Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
Table 1-6
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A40MX02-1PL68 IC FPGA MX SGL CHIP 3K 68-PLCC
A40MX02-1PLG68 IC FPGA MX SGL CHIP 3K 68-PLCC
GSA50DTBT-S273 CONN EDGECARD 100PS R/A .125 SLD
GMA50DTBT-S273 CONN EDGECARD 100PS R/A .125 SLD
GSA50DTAT-S273 CONN EDGECARD 100PS R/A .125 SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A40MX02-PL68M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 40MX Family 3K Gates 295 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 68-Pin PLCC 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 3K GATES 295 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 68-PLCC 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 57 I/O 68PLCC
A40MX02-PLG44 鍔熻兘鎻忚堪:IC FPGA 57I/O 44PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:ECP2 LAB/CLB鏁�(sh霉):1500 閭忚集鍏冧欢/鍠厓鏁�(sh霉):12000 RAM 浣嶇附瑷�:226304 杓稿叆/杓稿嚭鏁�(sh霉):131 闁€鏁�(sh霉):- 闆绘簮闆诲:1.14 V ~ 1.26 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:208-BFQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:208-PQFP锛�28x28锛�
A40MX02-PLG44I 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 44-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
A40MX02-PLG44M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 40MX Family 3K Gates 295 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 44-Pin PLCC 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 3K GATES 295 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 44PLCC - Rail/Tube 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 44-PLCC
A40MX02-PLG68 鍔熻兘鎻忚堪:IC FPGA 57I/O 68PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:ECP2 LAB/CLB鏁�(sh霉):1500 閭忚集鍏冧欢/鍠厓鏁�(sh霉):12000 RAM 浣嶇附瑷�:226304 杓稿叆/杓稿嚭鏁�(sh霉):131 闁€鏁�(sh霉):- 闆绘簮闆诲:1.14 V ~ 1.26 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:208-BFQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:208-PQFP锛�28x28锛�