tIRD1 FO = 1 " />

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    參數(shù)資料
    型號: A40MX02-FPLG44
    廠商: Microsemi SoC
    文件頁數(shù): 127/142頁
    文件大?。?/td> 0K
    描述: IC FPGA MX SGL CHIP 3K 44-PLCC
    標準包裝: 27
    系列: MX
    輸入/輸出數(shù): 34
    門數(shù): 3000
    電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 44-LCC(J 形引線)
    供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
    40MX and 42MX FPGA Families
    Re vi s i on 11
    1 - 81
    Input Module Predicted Routing Delays2
    tIRD1
    FO = 1 Routing Delay
    2.8
    3.1
    3.5
    4.1
    5.7
    ns
    tIRD2
    FO = 2 Routing Delay
    3.2
    3.5
    4.1
    4.8
    6.7
    ns
    tIRD3
    FO = 3 Routing Delay
    3.7
    4.1
    4.7
    5.5
    7.7
    ns
    tIRD4
    FO = 4 Routing Delay
    4.2
    4.6
    5.3
    6.2
    8.7
    ns
    tIRD8
    FO = 8 Routing Delay
    6.1
    6.8
    7.7
    9.0
    12.6
    ns
    Global Clock Network
    tCKH
    Input LOW to HIGH
    FO = 32
    FO = 635
    4.6
    5.0
    5.1
    5.6
    5.7
    6.3
    6.7
    7.4
    9.3
    10.3
    ns
    tCKL
    Input HIGH to LOW
    FO = 32
    FO = 635
    5.3
    6.8
    5.9
    7.6
    6.7
    8.6
    7.8
    10.1
    11.0
    14.1
    ns
    tPWH
    Minimum Pulse
    Width HIGH
    FO = 32
    FO = 635
    2.5
    2.8
    2.7
    3.1
    3.5
    3.6
    4.1
    5.1
    5.7
    ns
    tPWL
    Minimum Pulse
    Width LOW
    FO = 32
    FO = 635
    2.5
    2.8
    2.7
    3.1
    3.5
    3.6
    4.1
    5.1
    5.7
    ns
    tCKSW
    Maximum Skew
    FO = 32
    FO = 635
    1.0
    1.2
    1.3
    1.5
    2.2
    ns
    tSUEXT
    Input Latch
    External Set-Up
    FO = 32
    FO = 635
    0.0
    ns
    tHEXT
    Input Latch
    External Hold
    FO = 32
    FO = 635
    4.0
    4.6
    4.4
    5.2
    5.0
    5.9
    6.9
    8.2
    9.6
    ns
    tP
    Minimum Period
    (1/fMAX)
    FO = 32
    FO = 635
    9.2
    9.9
    10.2
    11.0
    11.1
    12.0
    12.7
    13.8
    21.2
    23.0
    ns
    fMAX
    Maximum
    Datapath
    Frequency
    FO = 32
    FO = 635
    108
    100
    98
    91
    90
    83
    79
    73
    47
    44
    MHz
    TTL Output Module Timing5
    tDLH
    Data-to-Pad HIGH
    3.6
    4.0
    4.5
    5.3
    7.4
    ns
    tDHL
    Data-to-Pad LOW
    4.2
    4.6
    5.2
    6.2
    8.6
    ns
    tENZH
    Enable Pad Z to HIGH
    3.7
    4.2
    4.7
    5.5
    7.7
    ns
    tENZL
    Enable Pad Z to LOW
    4.1
    4.6
    5.2
    6.1
    8.5
    ns
    tENHZ
    Enable Pad HIGH to Z
    7.34
    8.2
    9.3
    10.9
    15.3
    ns
    Table 1-39 A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
    (Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
    –3 Speed
    –2 Speed
    –1 Speed
    Std Speed –F Speed
    Parameter / Description
    Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
    Notes:
    1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
    2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
    estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
    3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
    can be obtained from the Timer utility.
    4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
    External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
    external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
    5. Delays based on 35 pF loading.
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