tINYH Pad-to-Y HIGH " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A40MX02-2PLG68I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 105/142闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA MX SGL CHIP 3K 68-PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 19
绯诲垪锛� MX
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 3000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 68-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 68-PLCC锛�24.23x24.23锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�鐣�(d膩ng)鍓嶇105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 61
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.4
1.6
1.8
2.1
2.9
ns
tINGL
G to Y LOW
1.4
1.6
1.8
2.1
2.9
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
1.8
2.0
2.3
2.7
4.0
ns
tIRD2
FO = 2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO = 3 Routing Delay
2.3
2.6
3.0
3.5
4.9
ns
tIRD4
FO = 4 Routing Delay
2.6
3.0
3.3
3.9
5.4
ns
tIRD8
FO = 8 Routing Delay
3.6
4.0
4.6
5.4
7.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
2.6
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
6.6
7.8
9.2
ns
tPWH
Minimum Pulse Width
HIGH
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
tPWL
Minimum Pulse Width
LOW
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.3
0.4
0.5
0.7
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 384
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
tP
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.6
5.8
6.4
9.7
10.7
ns
fMAX
Maximum Frequency FO = 32
FO = 384
237
215
195
198
179
172
156
103
94
MHz
Table 1-34 A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70掳C)
鈥�3 Speed
鈥�2 Speed
鈥�1 Speed
Std Speed
鈥揊 Speed
Units
Parameter / Description
Min. Max. Min. Max.
Min. Max. Min. Max. Min. Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A40MX02-2PQ100 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 100-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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