2-38 Revision 11 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enabl" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3PN250-Z2VQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 63/114闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 250K GATES 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 68
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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ProASIC3 nano DC and Switching Characteristics
2-38
Revision 11
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Figure 2-10 Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
TRIBUF
CLKBUF
INBUF
CLKBUF
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Pad
Out
CLK
Enable
Preset
Data_out
Data
EOUT
DOUT
Enable
CLK
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
D_Enable
A
B
C
D
E
F
G
H
I
J
L
K
Y
Core
Array
鐩搁棞(gu膩n)PDF璩囨枡
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