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ProASIC3 nano Flash FPGAs
Revision 11
2-25
3.3 V LVCMOS Wide Range
Table 2-33 Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range
3.3 V LVCMOS
Wide Range
Equivalent
Software
Default
Drive
Strength
Option3
VIL
VIH
VOL
VOH
IOL
IOH
IIL1
IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
A4
100 A
2 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2
100 100
10
100 A
4 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2
100 100
10
100 A
6 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2
100 100
10
100 A
8mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2
100 100
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
4. Currents are measured at 85掳C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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