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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3PN250-2VQ100
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 69/114闋�(y猫)
鏂囦欢澶у皬锛� 0K
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
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闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
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宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)鐣�(d膩ng)鍓嶇69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)绗�109闋�(y猫)绗�110闋�(y猫)绗�111闋�(y猫)绗�112闋�(y猫)绗�113闋�(y猫)绗�114闋�(y猫)
ProASIC3 nano DC and Switching Characteristics
2-44
Revision 11
Output Enable Register
Timing Characteristics
Figure 2-14 Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
tOESUE
50%
tOESUDtOEHD
50%
tOECLKQ
1
0
tOEHE
tOERECPRE
tOEREMPRE
tOERECCLR
tOEREMCLR
tOEWCLR
tOEWPRE
tOEPRE2Q
tOECLR2Q
tOECKMPWH tOECKMPWL
50%
Table 2-60 Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.44 0.51 0.59
ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36 0.42
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.22 0.25 0.30
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.22 0.25 0.30
ns
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
0.36 0.41 0.48
ns
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
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