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ProASIC3 nano Flash FPGAs
Revision 11
2-51
Timing Characteristics
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Table 2-65 Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
鈥�2
鈥�1
Std.
Units
INV
Y = !A
tPD
0.40
0.46
0.54
ns
AND2
Y = A B
tPD
0.47
0.54
0.63
ns
NAND2
Y = !(A B)
tPD
0.47
0.54
0.63
ns
OR2
Y = A + B
tPD
0.49
0.55
0.65
ns
NOR2
Y = !(A + B)
tPD
0.49
0.55
0.65
ns
XOR2
Y = A
Bt
PD
0.74
0.84
0.99
ns
MAJ3
Y = MAJ(A, B, C)
tPD
0.70
0.79
0.93
ns
XOR3
Y = A
B Ct
PD
0.87
1.00
1.17
ns
MUX2
Y = A !S + B S
tPD
0.51
0.58
0.68
ns
AND3
Y = A B C
tPD
0.56
0.64
0.75
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for
derating values.
Figure 2-21 Sample of Sequential Cells
DQ
DFN1
Data
CLK
Out
D
Q
DFN1C1
Data
CLK
Out
CLR
DQ
DFI1E1P1
Data
CLK
Out
En
PRE
D
Q
DFN1E1
Data
CLK
Out
En
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A3P125-2FG144 IC FPGA 1KB FLASH 125K 144-FBGA
EP4CE6E22C8LN IC CYCLONE IV FPGA 6K 144EQFP
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