參數(shù)資料
型號: A3PN125-2VQG100I
元件分類: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件頁數(shù): 31/106頁
文件大?。?/td> 3324K
代理商: A3PN125-2VQG100I
ProASIC3 nano DC and Switching Characteristics
2- 16
R e visio n 8
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-14 Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
I/O Standard
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option2
Slew
Rate
VIL
VIH
VOL
VOH
IOL
1 I
OH
1
Min.
V
Max
V
Min.
V
Max.
VMax. V
Min.
VmA mA
3.3 V LVTTL/
3.3 V
LVCMOS
8 mA
High –0.3
0.8
2
3.6
0.4
2.4
8
3.3 V
LVCMOS
Wide Range
100 A
8 mA
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2 100
A
100
A
2.5 V
LVCMOS
8 mA
High –0.3
0.7
1.7
3.6
0.7
1.7
8
1.8 V
LVCMOS
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45
4
1.5 V
LVCMOS
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
2
Notes:
1. Currents are measured at 85°C junction temperature.
2. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
Table 2-15 Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
DC I/O Standards
Commercial 1
Industrial 2
IIL
3
IIH
4
IIL
3
IIH
4
A
3.3 V LVTTL / 3.3 V LVCMOS
10
15
3.3 V LVCMOS Wide Range
10
15
2.5 V LVCMOS
10
15
1.8 V LVCMOS
10
15
1.5 V LVCMOS
10
15
Notes:
1. Commercial range (–20°C < TA < 70°C)
2. Industrial range (–40°C < TA < 85°C)
3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
相關PDF資料
PDF描述
A3PN125-2VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
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