Revision 11 2-23 Timing Characteristics Table 2-29 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commerci" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3PN125-2VQ100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 46/114闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA NANO 125K GATES 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�鐣�(d膩ng)鍓嶇46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�
ProASIC3 nano Flash FPGAs
Revision 11
2-23
Timing Characteristics
Table 2-29 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
9.70
0.04
1.13
1.52
0.43
9.88
8.82
2.31
2.50
ns
鈥�1
0.51
8.26
0.04
0.96
1.29
0.36
8.40
7.50
1.96
2.13
ns
鈥�2
0.45
7.25
0.03
0.84
1.13
0.32
7.37
6.59
1.72
1.87
ns
4 mA
Std.
0.60
9.70
0.04
1.13
1.52
0.43
9.88
8.82
2.31
2.50
ns
鈥�1
0.51
8.26
0.04
0.96
1.29
0.36
8.40
7.50
1.96
2.13
ns
鈥�2
0.45
7.25
0.03
0.84
1.13
0.32
7.37
6.59
1.72
1.87
ns
6 mA
Std.
0.60
6.90
0.04
1.13
1.52
0.43
7.01
6.22
2.61
3.01
ns
鈥�1
0.51
5.87
0.04
0.96
1.29
0.36
5.97
5.29
2.22
2.56
ns
鈥�2
0.45
5.15
0.03
0.84
1.13
0.32
5.24
4.64
1.95
2.25
ns
8 mA
Std.
0.60
6.90
0.04
1.13
1.52
0.43
7.01
6.22
2.61
3.01
ns
鈥�1
0.51
5.87
0.04
0.96
1.29
0.36
5.97
5.29
2.22
2.56
ns
鈥�2
0.45
5.15
0.03
0.84
1.13
0.32
5.24
4.64
1.95
2.25
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-30 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
7.19
0.04
1.13
1.52
0.43
7.32
6.40
2.30
2.62
ns
鈥�1
0.51
6.12
0.04
0.96
1.29
0.36
6.22
5.44
1.96
2.23
ns
鈥�2
0.45
5.37
0.03
0.84
1.13
0.32
5.46
4.78
1.72
1.96
ns
4 mA
Std.
0.60
7.19
0.04
1.13
1.52
0.43
7.32
6.40
2.30
2.62
ns
鈥�1
0.51
6.12
0.04
0.96
1.29
0.36
6.22
5.44
1.96
2.23
ns
鈥�2
0.45
5.37
0.03
0.84
1.13
0.32
5.46
4.78
1.72
1.96
ns
6 mA
Std.
0.60
4.57
0.04
1.13
1.52
0.43
4.64
3.92
2.60
3.14
ns
鈥�1
0.51
3.89
0.04
0.96
1.29
0.36
3.95
3.33
2.22
2.67
ns
鈥�2
0.45
3.41
0.03
0.84
1.13
0.32
3.47
2.93
1.95
2.34
ns
8 mA
Std.
0.60
4.57
0.04
1.13
1.52
0.43
4.64
3.92
2.60
3.14
ns
鈥�1
0.51
3.89
0.04
0.96
1.29
0.36
3.95
3.33
2.22
2.67
ns
鈥�2
0.45
3.41
0.03
0.84
1.13
0.32
3.47
2.93
1.95
2.34
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1A3P250-2VQ100 IC FPGA 1KB FLASH 250K 100-VQFP
A3P250-2VQG100 IC FPGA 1KB FLASH 250K 100-VQFP
A3PN125-2VQG100I IC FPGA NANO 125K GATES 100-VQFP
BR24T128FVJ-WE2 IC EEPROM I2C 128K 400KHZ 8TSSOP
AGLN060V2-ZVQG100I IC FPGA NANO 1KB 60K 100VQFP
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A3PN125-2VQG100 鍔熻兘鎻忚堪:IC FPGA NANO 125K GATES 100-VQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN125-2VQG100I 鍔熻兘鎻忚堪:IC FPGA NANO 125K GATES 100-VQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN125-DIELOT 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:A3PN125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
A3PN125-VQ100 鍔熻兘鎻忚堪:IC FPGA NANO 125K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN125-VQ100I 鍔熻兘鎻忚堪:IC FPGA NANO 125K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�